Many of today's computing applications such as cellular phones, digital cameras, and personal computers, use nonvolatile memories to store data or code. Nonvolatility is advantageous because it allows the computing system to retain its data and code even when power is removed from the computing system. Thus if the system is turned off or if there is a power failure, there is no loss of code or data.
One example of a nonvolatile memory device is the flash Electrically Erasable Programmable Read-only Memory (flash EEPROM or flash memory). Flash memory can be programmed by the user, and once programmed, the flash memory retains its data until the memory is erased. Electrical erasure of the flash memory erases the contents of the memory of the device in one relatively rapid operation. The flash memory may then be programmed with new code or data.
Flash memory customers often use programming equipment such as device programmers, automatic-test-equipment (ATE), and Joint Test Action Group (JTAG) programmers to program the memories. This equipment has hardware and software operating system overhead associated with sending programming information to the flash memory. The overhead, which provides time for the equipment to setup addresses and control signals, can range from 12 microseconds (μs) to 180 μs per byte/word or higher, depending on the equipment used.
Word or byte program operations in flash memory devices are typically executed by a multi-cycle command sequence. A ‘Program Set-up’ command is issued, followed by a second write that specifies the address and data. Control logic in the flash device, such as a Write State Machine (WSM), then takes over, controlling the program and program verify algorithms internally. While the WSM is working, the device can automatically enter ‘Read Status Register’ mode and remain there after the word/byte program is complete. The completion of the program event is indicated in status register. The status register can also indicate any errors.
FIG. 1 is flow diagram of typical program command sequence 100 of a prior art implementation. At step 110, the user sends a program command (‘Program Set-up’) and a program address to the flash memory. The ‘Program Set-Up’ command sets the Command User Interface (CUI) into a state such that the next write will load the address and data registers. The program address is the memory location to which the user wishes to write. The control logic in the memory receives that information and configures itself for program mode. The next write to the flash memory device after the ‘Program Set-Up’ command will cause the logic to latch the address and data and to begin the program algorithm. Then at step 120, the user sends the program data and the program address again. The control logic takes the data and program address and performs the program operation at the appropriate address in the memory array. The flash device switches to a read status mode where the device can output status register data. The user queries the status register at step 130. If the status register indicates that the program operation is not done, then the user waits and continues to poll the status register value. If the status register indicates that the program operation is done at step 130, the user can also check to see if the program was successful at step 140. For example, one possible cause of an unsuccessful program is incorrect program voltage. At step 150, the user decides whether there are more addresses to program. If there are, then the steps 110 through 150 have to be repeated.
FIG. 2 is a timing diagram 200 showing the relationship between the signals used in connection with the prior art program command sequence of FIG. 1. The timing diagram 200 includes six separate program sequences 210, 220, 230, 240, 250, 260. For this example, each program operation 210, 220, 230, 240, 250, 260 programs data to a different program address. In order to understand the operation of the program sequence 100 of FIG. 1, the operation of a single program operation 220 including the time periods T4, T5, and T6 will be discussed. FIG. 2 shows the signals referred to as ADDRESS 202, WRITE ENABLE 204, DATA 206, and STATUS 208 associated with the program sequence 100.
At time T4, the flash memory device is set up for programming as described above at step 110 of FIG. 1. Program address PA 221 is sent on the address bus ADDRESS 202 to the memory. The program command 225 is sent on the data bus DATA 206 to the control logic on the flash device. When the user is driving the program command 225 and the desired program address PA 221, WRITE ENABLE 204 is toggled. The WRITE ENABLE pulse 223 initiates the program and informs the control logic that an operation is requested. The control logic can read the command on DATA 206 and determine that a program is to occur at PA 221. The control logic prepares the flash memory for a program operation.
Then at time T5, the user sends the program address 222 and program data 226 to the flash memory. For this example, the first program address 221 and the second program address 222 are the same. At time T6, the user toggles WRITE ENABLE 204. This WRITE ENABLE pulse 224 causes the actual program to occur. The control logic uses the program address 222 and the program data 226 to program the appropriate address in the memory array.
During time T6, the user also polls the value on STATUS 208 to check the progress of the program operation. When STATUS 208 pulses to a logic high value, the program of data 226 to address 222 is complete. Other values in STATUS 208 can indicate a program failure.
The other instances 210, 230, 240, 250, 260 of the program operation are conducted in a similar fashion as that of the above described operation 220. Each program needs to have the program set up in order to a program an address. Hence, when more than one address location needs to be programmed, the program set up has to be repeated for each program operation. The signal setup time can become quite burdensome. A large amount of the time may not be consumed by the actual programming of the memory cells, but in setting up the memory device to enter program mode. Such overhead costs time and money to manufacturers and users.